je.st
news
Tag: soc
DesignCon Recognizes Altera for Outstanding FPGA and SoC Innovations
2014-02-04 06:00:00| Industrial Newsroom - All News for Today
Altera Wins Two 2014 DesignVision Awards for its 14 nm Stratix 10 FPGAs and SoCs and ARM DS-5 Altera Edition Toolkit for SoCs<br /> <br /> SAN JOSE, Calif. – Altera Corporation (NASDAQ: ALTR) today announced it received two DesignVision Awards at DesignCon 2014 for its innovations in FPGA and SoC technology. Altera's next-generation, 14 nm Stratix 10 FPGAs and SoCs won for best semiconductor and IP, and the ARM® Development Studio 5 (DS-5™) Altera Edition toolkit won for best ...This story is related to the following:Chip Sets | Integrated Circuits (IC) |
Tags: outstanding
soc
innovations
recognizes
Graphics SoC offers optimized rendering, interface count.
2014-01-29 14:28:57| Industrial Newsroom - All News for Today
Intended for automotive, building security, and industrial applications, MB86R24 combines ARM® Cortex™-A9 dual CPU core with embedded 2.5D and 3D graphics cores for accelerated processing and image rendering. There are 6 full HD input channels and 3 display output channels, and SoC affords flexible I/O control. Architecture is optimized for simultaneous use of all functional blocks, and harmonized structure permits simultaneous rendering of independent 2.5D and 3D graphics. This story is related to the following:Graphics Accelerators | I/O Processors
Tags: offers
count
graphics
interface
Dune HD selects Broadcom HD SoC for satellite set-top boxes
2014-01-28 14:30:38| Digital TV News
Broadcom (NASDAQ: BRCM) has announced that Dune HD has selected Broadcom's BCM7356 satellite system-on-a-chip (SoC) for its next generation set-top box (STB) deployments.
Tags: boxes
satellite
soc
selects
Interconnect Fabric IP cuts SoC development time.
2014-01-23 14:30:13| Industrial Newsroom - All News for Today
Embedded within FlexNoC interconnect IP fabric, FlexNoC Composition feature allows SoC architecture to be subdivided for implementation by various specialist design teams, each working independently on their own subsystem. Once all subsystems are complete, each can be integrated into one complete full chip-level FlexNoC interconnect fabric without requiring bridges. Unlike hybrid bus or crossbar, FlexNoC Composition re-connects each subsystem seamlessly through specialized low-latency protocol. This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores
Tags: time
development
fabric
cuts
EDA Software accelerates SoC verification closure.
2014-01-20 14:31:17| Industrial Newsroom - All News for Today
For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations. Support for SystemVerilog IEEE 1800-2012 real number modeling enables faster mixed-signal simulation. This story is related to the following:Electronic Design Automation (EDA) Software |
Tags: software
soc
verification
closure
Sites : [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] next »