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Silicon-Proven IP offers 16 nm FinFET Plus processes.

2015-04-16 14:31:06| Industrial Newsroom - All News for Today

DesignWare® PHY IP for TSMC's 16 nm FinFET Plus processes (16FF+GL and 16FF+LL) enables designers to accelerate development of SoCs that incorporate embedded memories and interface IP for USB 3.0/2.0 and HSIC; PCIe® 4.0/3.0/2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3; and LPDDR4/3/2 protocols. Also available, DesignWare Logic Libraries for TSMC 16FF+ processes include 7.5-, 9-, and 10.5-track libraries; power optimization kits; and High Performance Core (HPC) kits.

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