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ASIC Designer Concepteur ASIC
2015-06-19 01:08:35| Space-careers.com Jobs RSS
MDAs Digital Department is looking for engineers with experience in the design of large ASICs. These ASICs will be at the heart of a complex digital signal processing unit that will be part of new generation communication satellites. Knowledge of VHDL or Verilog and associated design tools for the preliminary FPGA implementation is essential. Candidates must have experience in ASIC synthesis timing analysis. Responsibilities Knowledge of Synplify, Xilinx Vivado,Modelsim, Synopsys DC Ultra, Synopsys PrimeTime Knowledge of UnixLinux environment and script languages CShell, Tcl Comfortable for doing lab debugging Exposure to space radiation effects on electronic components Knowledge of AMBA AXI4, CANBus, SpaceWire, 1553 digital busses, Serdes Familiarity with automated verification techniques for test benches Exposure to Microsemi Libero Designer, System Verilog, UVM Experience with communication systems Matlab Requirements Electrical Engineering EE or equivalent Bachelors degree Ten 10 years or more of experience designing ASICs Strong interpersonal skills and an ability to work well in a team. Excellent verbal and written communication skills in French and English. Le service numrique de MDA est la recherche dingnieurs avec une exprience en conception de grands ASIC. Ces ASIC seront au cur dun grand processeur de signaux numriques complexe qui fera partie des satellites de tlcommunications de la nouvelle gnration. La connaissance de VHDL ou de Verilog et des outils de conception connexes pour limplmentation prliminaire FPGA est essentielle. Les candidats doivent avoir de lexprience en synthse ASIC et en analyse de temps. Responsabilits Connaissance de Synplify, Xilinx Vivado,Modelsim, Synopsys DC Ultra, Synopsys PrimeTime Connaissance de lenvironnement UnixLinux et des langages de script CShell, Tcl laise effectuer du dbogage de laboratoire Exposition aux effets du rayonnement spatial sur les composants lectroniques Connaissance dAMBA AXI4, CANBus, SpaceWire, 1553 digital busses, Serdes Familiarit avec les techniques de vrification automatises pour les bancs dessai Exposition Microsemi Libero Designer, System Verilog, UVM Exprience avec les systmes de communication Matlab Exigences Baccalaurat en gnie lectrique ou quivalent Dix 10 ans ou plus dexprience en conception ASIC Excellentes habilets en communications interpersonnelles et capacit de bien travailler en quipe. Excellentes aptitudes communiquer en franais et en anglais, loral et lcrit.
Tags: designer
asic
concepteur
ASIC seeks right to deny financial licences
2015-03-23 08:32:03| Automakers - Topix.net
As the Australian Securities and Investments Commission calls for an overhaul of its government funding model to a user pays system, it has also asked for increased powers for product intervention, the right to deny financial licence applications, and to prosecute managers who fail to properly supervise their employees. ASIC chairman Greg Medcraft said that improving the integrity and quality of financial advice remained the regulator's number one priority.
Tags: financial
seeks
deny
licences
ASIC complex product clampdown embroils banks
2015-02-24 09:20:39| Automakers - Topix.net
ASIC's concerns centre on a group of 10 licensees of such products including HSBC, Westpac Banking Corp, Commonwealth Bank of Australia's subsidiary Count Financial, Genesys Wealth Advisers, and Madison Financial Group. Photo: Jim Rice The corporate regulator is applying more pressure on providers of complex financial products, in a clampdown that has embroiled several large banks.
Tags: product
complex
banks
asic
Logic Cell Device supports ASIC and complex SOC prototyping.
2015-01-19 14:30:45| Industrial Newsroom - All News for Today
With capacity of 50 million equivalent ASIC gates, Virtex® UltraScale™ VU440 FPGA leverages UltraScale architecture's ASIC-like clocking, next-generation routing, and logic block enhancements, making it suited for ASIC prototyping and large scale emulation. Device delivers 4.4 M logic cells, 1,456 user I/Os, 48 x 16.3 Gbps backplane-capable transceivers, and 89 Mb block RAM. Production qualified at 28nm node, and SSI technology uses TSMC's CoWoS 3D IC process to achieve maximum silicon scaling.
Tags: cell
complex
device
supports
Life insurers brace for ASIC report
2014-10-06 13:14:23| Automakers - Topix.net
Australia's biggest life insurers are bracing ahead of the release of a report from the corporate watchdog, slated for release this week. It is expected to be damning of the exorbitant commission fees the industry offers financial planners to sign customers up to their policies.
Tags: life
report
insurers
brace