Implementing enhanced version of ARCv2DSP instruction set architecture, DesignWare® ARC® EM9D and EM11D Processors combine RISC and DSP processing with support for XY memory system. Devices enable sustained throughput of one 32 x 32 MAC operation or two 16 x 16 MAC operations per clock cycle with minimal energy and area overhead. Processors also support full integer, fractional divide, and square root operations as well as unaligned loads/stores and bitstream parsing.