TimingDesigner v9.4, integrated with Cadence® Allegro® Sigrity™ SI solution, provides automated timing closure environment for DDRx interface design and sign-off. Specifically, integration allows Sigrity to automatically export cycle-accurate timing simulation results to TimingDesigner for graphical viewing and analysis. Solution combines power-aware sign-off-level simulation accuracy with fully parameterized timing diagrams.
This story is related to the following:Computer Aided Software Engineering (CASE) Software | Simulation Software