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Interface IP supports mobile and multimedia SoC designs.

2013-09-26 14:31:23| Industrial Newsroom - All News for Today

Based on TSMC's 20 nm SoC process technology,  DesignWare® USB, DDR, PCI Express, and MIPI PHY IP help designers minimize power consumption and optimize performance for mobile and multimedia SoC designs used in tablets and smartphones. TSMC's double patterning mask technology on 20SoC process utilizes 2 photo masks, each with half pattern, to enable printing of images below node's minimum spacing design rules. This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores

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