To maximize data reliability without additional error correction chips, 4 Mb asynchronous Static Random Access Memory (SRAM) integrates hardware Error-Correcting Code (ECC) that block performs all error correction functions inline, without user intervention, for Soft Error Rate (SER) performance of <0.1 FIT/Mb. Optional error indication signal indicates correction of single-bit errors. Other features include x8 and x16 configurations as well as Fast, MoBL, and Fast with PowerSnooze™ options.