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Asynchronous SRAMs offer on-chip Error Correcting Code.

2015-04-29 14:31:08| Industrial Newsroom - All News for Today

To maximize data reliability without additional error correction chips, 4 Mb asynchronous Static Random Access Memory (SRAM) integrates hardware Error-Correcting Code (ECC) that block performs all error correction functions inline, without user intervention, for Soft Error Rate (SER) performance of <0.1 FIT/Mb. Optional error indication signal indicates correction of single-bit errors. Other features include x8 and x16 configurations as well as Fast, MoBL, and Fast with PowerSnooze™ options.

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