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On-Chip Network enhances SoC design based on physical synthesis.
2015-06-25 14:31:06| Industrial Newsroom - All News for Today
Expanding on interleaved multi-channel technology (IMT), SonicsGN® 3.0 includes layout optimization features for design flows based on physical synthesis as well as place and route tools. SoC designers can eliminate multi-channel DRAM access bottlenecks with IMT and reduce layout tool iterations with flexible user control of hierarchical RTL partitioning and re-timing stage insertion. Also included, flexible reordering buffer architecture enhances concurrency.
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