Accelerating runtimes and optimizing QoR, Vivado® Design Suite 2014.1 automates UltraFast™ design methodology best practices for 28 nm 7 series and 20 nm UltraScale™ All Programmable devices. Software automates correct-by-construction constraints with interactive timing constraint wizard. Vivado High-Level Synthesis provides hardware acceleration of OpenCL kernels and enables C, C++, and System C specifications to be directly targeted into devices without need to manually create RTL.
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