To enable accelerated and predictable design cycles, Vivado Design Suite 2013.3 automates critical aspects of UltraFast™ design methodology, delivering design rule checks that guide engineers throughout design cycle. System-wide co-optimization of design and Xilinx IP enables designers to share clocking resources throughout design with connectivity IP such as Ethernet MAC or PCIe®. By dynamically swapping functions on demand, Partial Reconfiguration technology maximizes usage of device resources.
This story is related to the following:Electronic Design Automation (EDA) Software