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LPDDR4 PHY Layer Test Software completely assesses conformance.
2014-09-29 14:31:32| Industrial Newsroom - All News for Today
PHY layer and conformance test solution for JEDEC LPDDR4 mobile memory technology provides all tools needed to qualify LPDDR4 designs. Through automated set-up and test execution, solution can reduce testing cycles to 1 hr. Functionality ensures designs are in full conformance with memory standards. If memory system fails conformance tests, user can switch to debug mode and use tools to isolate events of interest for deeper root-cause analysis with DPOJET Jitter and Eye measurement toolkit.<br /> This story is related to the following:SoftwareCommunications Testers | Trouble Shooting Software | CAE Software
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test
completely
layer
Broadcom Enables Industry's First 20 nm 100G Coherent PHY
2014-09-23 13:56:06| wirelessdesignonline News Articles
Broadcom Corporation (NASDAQ: BRCM), a global innovation leader in semiconductor solutions for wired and wireless communications, today announced that its high performance 20 nanometer (nm) signal processing enhanced mixed signal technologies has enabled NTT Electronics' new NLD0640 100G coherent digital signal processor (DSP) — an industry first. Optimized for use in 100G-and-beyond optical fiber communication systems, the Broadcom-enabled coherent physical layer transceiver (PHY) consumes less than half the power of existing long-haul coherent ICs and expands the use of coherent technology to metro and shorter reach links.
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phy
Mult-Rate 100GbE Gearbox PHY features monolithic construction.
2014-09-19 14:31:05| Industrial Newsroom - All News for Today
Optimized for next-generation cloud-scale data center, enterprise, and core networks, BCM82792 offers dual 100 Gbps ports on single gearbox chip, operates at 2 W per port, and supports CR4 and SR4 links. This 28 nm CMOS PHY can multiplex and demultiplex data across eight 25 Gbps channels to or from twenty 10 Gbps channels. Additionally, configuration allows support of 8 bi-directional lanes at 10 Gbps for 10GbE or 40GbE pass-through applications. This story is related to the following:Computer Hardware and PeripheralsSearch for suppliers of: Transceivers |
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construction
phy
monolithic
Cadence Achieves PCIe 3.0 Compliance for PHY and Controller IP
2014-07-29 06:00:00| Industrial Newsroom - All News for Today
SAN JOSE, Calif. — Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that its PHY IP and Controller IP for PCI Express® (PCIe®) 3.0 have passed certification tests from PCI-SIG®. The solutions were tested to their full potential and complied with the full speed of 8GT/s for PCIe 3.0 technology. The compliance assures designers that their system-on-chip (SoC) designs will operate as expected.<br /> <br /> "As a PCI-SIG member for more than 10 ...This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores
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DDR4 PHY IP targets microserver market.
2014-05-28 14:31:47| Industrial Newsroom - All News for Today
Built on 16 nm FinFET process, Cadence® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize maximum performance of DDR4 standard, which is specified to scale up to 3,200 Mbps. This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores