In addition to power optimization features added to instruction set architecture and power scaling unit, CEVA-TeakLite-4 v2 includes 50 added instructions, 64-bit data processing support, and scalable data bandwidth up to 128-bit. System interface spans from low-power AHB bus to high-performance AXI bus with various master/slave configurations. Architecture framework is deployed across family of CEVA-TeakLite-4 cores, namely CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421.
This story is related to the following:Digital Signal Processors (DSP)