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Efficiency-Optimized Processor Core suits low-power devices.

2013-04-30 14:35:06| Industrial Newsroom - All News for Today

Available in sizes as small as 12K gates, AndesCore™ N7 (Hummingbird) 32-bit processor series implements AndeStar™ V3m architecture in 2-stage pipeline for optimal efficiency of 108 DMIPS/mW. IP cores come with complete software development environment and libraries and incorporate mechanisms that provide for acceleration of applications that utilize higher-latency flash memory. Products in this series are fully supported by integrated GCC tools environment. This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores

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