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Verification IP optimizes FPGA and SoC design reliability.

2015-03-11 13:31:08| Industrial Newsroom - All News for Today

Supporting FPGA and SoC designs based on ARM AMBA 4 architecture, plug-and-play AXI4 Verification IP was developed in SystemVerilog and is available for OVM, VMM, and UVM verification methodologies. Reusable, configurable, and pre-verified, AXI4 VIP supports functional coverage for checkers to ensure IP/RTL behavior is continuously monitored. For faster debug cycles, solution includes features such as Transaction Tracker and Bandwidth Monitor.

Tags: design reliability soc verification

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