Home Verification IP targets low-power memory controllers.
 

Keywords :   


Verification IP targets low-power memory controllers.

2014-12-17 14:31:30| Industrial Newsroom - All News for Today

Based on 100% native SystemVerilog Universal Verification Methodology architecture, Synopsys VIP for LPDDR4 comes with verification plans, built-in coverage, and protocol-aware memory debug environment. Transactor and monitor functions provide set of protocol, methodology, verification, and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs. VIP can also be dynamically configured to model any memory vendor component without need to recompile.

Tags: memory targets verification controllers

Category:Industrial Goods and Services

Latest from this category

All news

31.10Consolidated Financial Statements for the six-month period ended September 30, 2024
31.10Notice regarding the revision of the business results forecasts
Industrial Goods and Services »
05.11Registration Now Open for RadTech 2025
05.11Atlantic Tropical Weather Outlook
05.11Eastern North Pacific Tropical Weather Outlook
05.11Tropical Storm Rafael Graphics
05.11Tropical Storm Rafael Public Advisory Number 7A
05.11Summary for Tropical Storm Rafael (AT3/AL182024)
05.11Vodafone-Three merger could get green light, watchdog says
05.11Altice USA residential video RGUs down 77,000 in 3Q 2024
More »