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Verification IP targets low-power memory controllers.

2014-12-17 14:31:30| Industrial Newsroom - All News for Today

Based on 100% native SystemVerilog Universal Verification Methodology architecture, Synopsys VIP for LPDDR4 comes with verification plans, built-in coverage, and protocol-aware memory debug environment. Transactor and monitor functions provide set of protocol, methodology, verification, and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs. VIP can also be dynamically configured to model any memory vendor component without need to recompile.

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