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IC Packaging Design/Analysis Solution offers all necessary tools.

2016-03-21 13:31:04| Industrial Newsroom - All News for Today

Focused on advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs, IC packaging design and analysis solution includes Cadence® OrbitIO™ Interconnect Designer, Cadence System-in-Package (SiP) Layout, and Cadence Physical Verification System (PVS). Capabilities enable multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.

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