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ASIC Verification engineer
2015-11-09 20:05:16| Space-careers.com Jobs RSS
MDAs Digital Department is looking for engineers with experience in verification of large ASICs. These ASICs will be at the heart of a complex digital signal processing unit that will be part of new generation communication satellites. Knowledge of VHDL, Verilog, SVA and SystemVerilog and associated design tools for the preliminary FPGA implementation is essential. Candidates must have experience in a UVM validation environment. Responsibilities Knowledge of Synplify, Xilinx Vivado including IP integration flow, Matlab, Matlab SYSGEN, Modelsim, Synopsys DC Ultra, Synopsys PrimeTime Knowledge of UnixLinux environment, script languages CShell, Tcl and makefiles Familiarity with automated verification techniques for test benches and revision control SVN Jenkins Comfortable for doing lab debugging Exposure to space radiation effects on electronic components Knowledge of AMBA AHB, CANBus, SpaceWire, 1553 digital busses, Serdes Experience with communication systems Requirements Electrical Engineering EE or equivalent Bachelors degree Ten 10 years or more of experience designing ASICs, with a minimum of 5 years in ASIC verification Strong interpersonal skills and an ability to work well in a team. Excellent verbal and written communication skills in French and English. Able to multitasks.
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