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Tag: verification
HyperLynx Alliance Accelerates High-Speed Design-Ins and Verification
2015-01-30 11:30:48| Industrial Newsroom - All News for Today
Mentor Graphics and Key Industry Partners Align Analysis Tools, Methodologies, Models, and Reference Designs SANTA CLARA, Calif., -- DESIGN CON 2015 -- HyperLynx Alliance Program Highlights -- HyperLynx Alliance formed by Mentor Graphics and key industry partners provides free access to virtual reference...
Tags: alliance
verification
accelerates
highspeed
Verification Software supports testing on VxWorks platforms.
2014-12-19 14:31:14| Industrial Newsroom - All News for Today
Integrated with Wind River® VxWorks® 7 RTOS, LDRA Tool Suite delivers object code verification that confirms compiler optimizations have not inadvertently introduced aberrant application code behavior. Software provides high-assurance data and control coupling analysis that is mandated in safety- and security-critical standards, such as DO-178C and ISO 26262. It can support and verify both simulated and target hardware without compromising application behavior or performance.
Tags: software
testing
supports
platforms
Biometric Fingerprint Reader offers fast, accurate verification.
2014-12-17 14:31:31| Industrial Newsroom - All News for Today
Accommodating such projects as National ID programs that need to store fingerprint template, Hamster Pro Duo/CL™ combines contactless smart card reader with optical fingerprint reader that is FAP 20 Mobile ID and PIV certified. FBI-Certified U20™ USB fingerprint sensor, with respective platen size and effective sensing areas of 18.2 x 22.9 mm and 15.24 x 20.32 mm, offers image resolution of 500 dpi and size of 300 x 400 pixels. Fingerprint Capture Speed is 0.2–0.5 sec with Smart Capture™.
Tags: fast
offers
reader
accurate
Verification IP targets low-power memory controllers.
2014-12-17 14:31:30| Industrial Newsroom - All News for Today
Based on 100% native SystemVerilog Universal Verification Methodology architecture, Synopsys VIP for LPDDR4 comes with verification plans, built-in coverage, and protocol-aware memory debug environment. Transactor and monitor functions provide set of protocol, methodology, verification, and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs. VIP can also be dynamically configured to model any memory vendor component without need to recompile.
Tags: memory
targets
verification
controllers
Verification IP supports PCIe 4.0.
2014-12-16 14:32:23| Industrial Newsroom - All News for Today
With design-aware Mentor® EZ-VIP PCI Express Verification IP, engineers can reduce time spent building test benches for ASIC and FPGA design verification. PCIe EZ-VIP includes pre-packaged verification environments for serial and parallel interfaces of PCIe 1.0, 2.0, 3.0, 4.0, and mPCIe, which can be used to verify PHY, Root Complex, and Endpoint designs. Test plans, compliance tests, test sequences, and protocol coverage are included as SV and XML source code.
Tags: supports
verification
pcie
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