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Tag: verification
BER Test Solution accelerates design verification.
2014-01-28 14:35:38| Industrial Newsroom - All News for Today
Scalable and expandable to meet future test needs, J-BERT M8020A enables accurate receiver characterization, validation, and compliance testing of single- and multi-lane devices. Unit supports 1–4 BERT channels and offers data rates up to 8.5 Gbps and 16 Gbps, with extension to 32 Gbps. Controlled from user interface via USB, tester offers built-in jitter injection, 8-tap de-emphasis, interference sources, reference clock multiplication, clock recovery, and equalization. This story is related to the following:Telecommunications Testers | Functional Testers | Testers | Data Communication Testers
Tags: design
test
solution
verification
Facebook Losing Users; 30 Years of Mac Ads; Snapchat 'Ghost' Verification
2014-01-23 19:34:15| PC Magazine Security Product Guide
Topping tech headlines Wednesday, Facebook usership is on the decline, celebrating Apple's Mac through commercials, and Snapchat rolls out a "ghost" verification screen.
Facebook Losing Users; 30 Years of Mac Ads; Snapchat 'Ghost' Verification
2014-01-23 19:34:15| PC Magazine Software Product Guide
Topping tech headlines Wednesday, Facebook usership is on the decline, celebrating Apple's Mac through commercials, and Snapchat rolls out a "ghost" verification screen.
Facebook Losing Users; 30 Years of Mac Ads; Snapchat 'Ghost' Verification
2014-01-23 17:34:59| PC Magazine Cell Phones Product Guide
Topping tech headlines Wednesday, Facebook usership is on the decline, celebrating Apple's Mac through commercials, and Snapchat rolls out a "ghost" verification screen.
EDA Software accelerates SoC verification closure.
2014-01-20 14:31:17| Industrial Newsroom - All News for Today
For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations. Support for SystemVerilog IEEE 1800-2012 real number modeling enables faster mixed-signal simulation. This story is related to the following:Electronic Design Automation (EDA) Software |
Tags: software
soc
verification
closure
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